The invention relates to a method for synchronizing a clock signal with a reference signal with the aid of a phase locked loop.
In a digital transmission system, a transmitter uses a transmission channel to transmit a data word according to a transmission clock to a receiver. In order to be able to recover the digitally transmitted word from a received signal sequence, the receiver needs the transmission clock signal with which the word was transmitted. Since this clock signal is not concomitantly transmitted in many applications, the receiver must reconstruct the clock signal from the received signal sequence. Therefore a transmitted signal sequence generally includes a synchronization part which is placed in front of the data part. In this case, the receiver can reconstruct the transmission clock signal from the signal sequence, which is typically effected with the aid of a phase locked loop. These signal sequences are often standardized and cannot be arbitrarily configured by the user.
A special signal sequence which is used, for example, in remotely controllable central locking systems in motor vehicles and which includes a code for opening or closing the vehicle in the data part is illustrated in FIG. 1. The signal sequence 50 includes a first synchronization part 53, a pause, a second synchronization part 54 and data words 55 which comprise, for example, a code for opening a vehicle. The synchronization parts 53, 54 include a bit sequence which is also present in the transmission clock. The clock period of this transmission clock is denoted TZ below. A length TP of the pause 51 is equal to an integer multiple of the transmission clock period TZ plus a fraction of the transmission clock period TZ. The time t1 denotes the beginning of the pause 51 and the time t2 denotes the end of the pause 51.
The two synchronization parts 53, 54 form the reference signal x which is interrupted by the pause 51 and can be used by a phase locked loop (not illustrated in FIG. 1), which is arranged at the receiver end, to reconstruct the transmission clock signal. The reconstructed clock signal is available at the output of the phase locked loop and is at the same frequency and has the same phase as the reference signal x.
In a conventional phase locked loop, the reconstructed transmission clock signal at the output of the phase locked loop is adjusted, during the first synchronization part 53 of the reference signal x, until its phase and frequency match the phase and frequency of the transmitted reference signal x. This adjustment results in a transient process during which the frequency of the reconstructed clock signal can vary slightly. During the pause 51 in the reference signal, regulation is interrupted and the clock signal at the output of the phase locked loop oscillates at that frequency and with that phase which it had at the beginning t1 of the pause 51. However, after the end t2 of the pause 51, regulation of the output signal is intended to be continued again. If the length TP of the pause were an integer multiple of the clock period TZ of the reference signal, it would be necessary to correct at most one small regulation error in the phase during the second synchronization part. However, since the length of the pause is a noninteger multiple of the clock period TZ, the clock signal and the reference signal x have a relatively large phase difference at the beginning of the second synchronization part, which in turn results in a relatively long transient regulation process during which the frequency of the output signal from the phase locked loop also changes.
This transient process when adjusting the phase difference is inevitably present in the known phase locked loops and is justified by the principle of feedback. However, there is a need for a method for synchronizing a clock signal with a reference signal and for a corresponding phase locked loop, which provides a good stabilization process in the event of a sudden phase change in the reference signal.